1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device and manufacturing method thereof. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for minimizing point defect caused by a deficiency in thin film transistors.
2. Discussion of the Related Art
A liquid crystal display (LCD) device is driven by utilizing the optical anisotropy and the polarization characteristics of liquid crystal. In general, the LCD device includes two substrates that are spaced apart and face into each other, and a liquid crystal layer interposed between the two substrates. Each of the substrates includes electrodes that face into each other, wherein a voltage applied to each electrode induces an electric field perpendicular to the substrates between the electrodes. An alignment of liquid crystal molecules of the liquid crystal layer is changed by varying an intensity or direction of the applied electric field. Accordingly, the LCD device displays an image by varying light transmittance through the liquid crystal material layer in accordance with the arrangement of the liquid crystal molecules. The LCD device has characteristics of excellent light transmittance and aperture ratio.
An LCD device including thin film transistors and pixel electrodes of a matrix form, which is referred to as an active matrix LCD (AM-LCD) device, is widely used due to its high resolution and fast moving images.
FIG. 1 is an expanded perspective view of a liquid crystal display device according to the related art. In FIG. 1, an LCD device has first and second substrates 5 and 10, which are spaced apart from and facing into each other, and a liquid crystal layer 11 interposed between the first and second substrates 5 and 10.
The first substrate 5 includes a black matrix 6, a color filter layer 7, and a transparent common electrode 9 subsequently disposed on the surface of the color filter layer. The black matrix 6 has an opening such that the color filter layer 7 corresponds to the opening of the black matrix 6 and includes three sub-color filters of red (R), green (G), and blue (B).
A gate line 14 and a data line 26 are formed on the inner surface of the second substrate 10, whereby the gate line 14 and the date line 26 cross each other to define a plurality of pixel areas P, and a thin film transistor T is formed at each intersection of the gate line 14 and the data line 26. The thin film transistor T is composed of a gate electrode, a source electrode, and a drain electrode. A transparent pixel electrode 32, which is connected to the thin film transistor T, is formed within the pixel area P and corresponds to the sub-color filters. In addition, the pixel electrode 32 is formed of a light transparent conductive material, such as indium-tin-oxide (ITO). The second substrate 10 may be commonly referred to as an array substrate.
Since the operation of the thin film transistor is important to the LCD device, characteristics of the thin film transistor should be improved. For example, current that flows through the channel of the thin film transistor is proportional to a channel length over a channel width, and thus the current can be increased by shortening a channel length and widening a channel width of the thin film transistor.
FIG. 2 is a plane view of an array substrate for a liquid crystal display device according to the related art, and FIG. 3 is an enlarged plane view of region “A” of FIG. 2. In FIGS. 2 and 3, a plurality of gate lines 14 are formed to be spaced apart in a first direction on a substrate 10, and a plurality of data lines 26 are formed in a second direction to cross the gate lines 14 to define a pixel area P. A thin film transistor T is formed at the intersection of the gate and data lines 14 and 26 to function as a switching element. The thin film transistor T is composed of a plurality of gate electrodes 12 connected to the gate lines 14 and receiving scanning signals, a plurality of source electrodes 22 connected to the data lines 26 and receiving data signals, and a plurality of drain electrodes 24 spaced apart from the source electrodes 22. The thin film transistor T further includes a semiconductor layer 18 between the gate electrode 12 and the source and drain electrodes 22 and 24.
A transparent pixel electrode 32 is formed in the pixel area P and is connected to the drain electrode 24. The pixel electrode 32 overlaps the gate line 14 to form a storage capacitor.
Here, the source and drain electrodes 22 and 24 are spaced apart over the gate electrode 12. The source electrode 22 extended from the data line 26 has a U-shape, and encloses a part of the drain electrode 24. The drain electrode 24 may have a first part that is surrounded by the source electrode 22 and a second part that is located at the pixel electrode 32. The first part has a rod shape, and the second part is larger than the first part.
Therefore, a channel CH between the source and drain electrodes 22 and 24 has a U-shape, and a current flowing through the channel is increased because a length L of the channel gets shorter and a width W of the channel grows wider.
Meanwhile, the semiconductor layer 18 consists of an active layer 18a over the gate electrode 12, a first extended portion 18b under the drain electrode 24, and a second extended portion 18c under the data line 26.
The first extended portion 18b of the semiconductor layer 18 rapidly becomes narrow toward the second part of the drain electrode 24 passing by one side of the gate electrode 12. Therefore, the first extended portion 18b of the semiconductor layer 18 is exposed in the region B that is outside the gate electrode 12. The drain electrode 24 may be disconnected by an etchant for patterning the source and drain electrodes 22 and 24 due to the exposed portion of the semiconductor layer 18.
FIGS. 4A to 4C and FIGS. 5A to 5C show the sequential process steps for methods of fabricating an array substrate according to the related art. FIGS. 4A to 4C are cross-sectional views taken along line IV-IV of FIG. 2, and FIGS. 5A to 5C are cross-sectional views taken along line V-V of FIG. 3.
In FIGS. 4A and 5A, a gate electrode 12 and a gate line 14 connected to the gate electrode 12 are formed on a substrate 10 by depositing and patterning a first metal layer. The gate line 14 and the gate electrode 12 are made of a metal material, such as aluminum (Al), an aluminum alloy of aluminum and neodymium (Nd), molybdenum (Mo), tungsten (W), and chromium (Cr). The gate line 14 and the gate electrode 12 may be formed of a double layer using aluminum or an aluminum alloy and molybdenum or chromium.
Aluminum having a relatively low electrical resistivity is widely used as a material of the gate line 14 and the gate electrode 12 to minimize RC delay. However, since aluminum may be easily corroded by acid during a fabrication process and may cause hillock in a later process under a high temperature condition, the gate line 14 may be disconnected. Thus, the gate line 14 and the gate electrode 12 may be formed of an alloy or a double layer including aluminum.
A gate insulating layer 16 is formed on the substrate 10 having the gate line 14 and the gate electrode 12 formed thereon by depositing an inorganic insulating material, such as silicon nitride (SiNx) and silicon oxide (SiO2), or by coating an organic insulating material, such as benzocyclobutene (BCB) and acrylic resin.
Subsequently, a semiconductor layer 18 and a doped semiconductor layer 20c are formed on the gate insulating layer 16 over the gate electrode 12. The semiconductor layer 18 is made of amorphous silicon and the doped semiconductor layer 20c is made of doped amorphous silicon.
As shown in FIGS. 4B and 5B, a data line 26, a source electrode 22, and a drain electrode 24 are formed by depositing and patterning a second metal layer. The data line 26, the source electrode 22, and the drain electrode 24 may be made of the metal material described above. Next, the doped semiconductor layer 20c of FIG. 4A, exposed between the source and drain electrodes 22 and 24, is removed to form an ohmic contact layer 20. As described above, the semiconductor layer 18 is composed of an active layer 18a over the gate electrode 12, a first extended portion 18b under the drain electrode 24, and a second extended portion 18c under the data line 26. The ohmic contact layer 20 consists of a first portion 20a corresponding to the drain electrode 24 and a second portion 20b corresponding to the data line 26 and the source electrode 22.
Although it is not shown in the drawings, the source electrode 22 has a U-shape, and the drain electrode 24 has a first part of a rod shape and a second part larger than the first part. The source electrode 22 surrounds the first part of the drain electrode 24. The first extended portion 18b of the semiconductor layer 18 gets rapidly narrow toward the second part of the drain electrode 24 passing one side of the gate electrode 12, and the first extended portion 18b of the semiconductor layer 18 is exposed at both sides of the drain electrode 24 in the rapidly narrowing region B. In region B where the first extended portion 18b is exposed, there is a metal pattern. More specifically, the drain electrode 24 is disposed over the semiconductor layer 18 in region B. An etchant may remain in region B after patterning the source and drain electrodes 22 and 24, and thus the drain electrode 24 may be disconnected due to the remaining etchant.
Meanwhile, in a region where the data line 26 is located, the second extended portion 18c of the semiconductor layer 18 forms a step and prevents the etchant from flowing under the data line 26. Therefore, the data line 26 is hardly affected by the etchant and is not disconnected.
Next, as shown in FIGS. 4C and 5C, a passivation layer 28 is formed on the substrate 10 including the source and drain electrodes 22 and 24 by coating a transparent organic material, such as benzocyclobutene (BCB) and an acrylic resin, or by depositing an inorganic material, such as silicon nitride (SiNx) and silicon oxide (SiO2). The passivation layer 28 is patterned, and a drain contact hole 30 exposing the drain electrode 24 is formed. A pixel electrode 32 is formed in a pixel area P on the passivation layer 28 by depositing a transparent conductive material, such as indium-tin-oxide (ITO) and indium-zinc-oxide (IZO), and by patterning the transparent conductive material. The pixel electrode 32 is connected to the drain electrode 24 through the drain contact hole 30.
However, in the LCD device including the above-described array substrate, the drain electrode may be disconnected due to the etchant in the region where the semiconductor layer is exposed.